1. Field of the Invention
This invention relates generally to semiconductor ceramic packages composed of a plurality of laminated insulator layers, and more particularly to such a semiconductor ceramic package having a power plane and a ground plane on internal insulator layers respectively and thermal vias for thermal dissipation beneath a semiconductor chip mounting portion thereof on which a semiconductor chip is mounted.
2. Description of the Prior Art
A semiconductor ceramic package on which a semiconductor chip is mounted has conventionally been provided with through holes or via holes formed beneath a semiconductor chip mounting portion for the purpose of improvement of thermal dissipation characteristic. The via holes are filled with a metal paste having high thermal conductivity, such as tungsten or silver, so that thermal vias are constituted. As shown in FIGS. 10 to 12, conventional thermal vias 4 are formed so as to be at an independent potential from a power plane 1 and a ground plane 2. Alternatively, the thermal vias 4 are connected to the ground plane 2 so as to be at a ground potential as shown in FIGS. 13 to 15. In each case, heat generated by operation of the semiconductor chip is efficiently conducted through the thermal vias 4 to the back surface of the package. The thermal vias 4 are usually independent electrically and insulated from other conductive patterns and pattern connecting vias (through holes). Alternatively, all the thermal vias 4 are connected together so as to be at the same potential and in some cases, further connected to the ground so as to be at a ground potential. Publication Nos. 3-286590 and 4-35053 of Japanese unexamined patent applications disclose the above-described conventional arrangement.
Reduction in resistance and impedance of an electrical power system of the package has recently become an important problem due to high speed operation of the semiconductor chip. For example, in semiconductor chips having a low input impedance, such as emitter-coupled logic (ECL), the potential of the electrical power system is varied by voltage drop due to high resistance of the power system, which results in malfunction of the chip. Furthermore, when the inductance of the electrical power system is high, particularly, in microprocessing units (MPU), the switching of the semiconductor chip causes fluctuation of the potential of the electrical power system of the package, which fluctuation is referred to as "ground bounce."
The prior art has proposed the following measures to prevent the malfunction of the semiconductor chip and occurrence of the ground bounce in the above-described type semiconductor ceramic packages. First, the semiconductor ceramic package wirings are designed so that the resistance at the power system is lowered as much as possible for prevention of voltage drop and so that the inductance of the power system is reduced for prevention of occurrence of the ground bounce. Second, a capacitance is provided between a power supply and the ground as measures against the ground bounce.
In the semiconductor ceramic packages having the thermal vias, however, these thermal vias are formed beneath the semiconductor chip mounting portion so as to penetrate through the package. Accordingly, the above-described measures cannot be taken for the semiconductor ceramic packages for the following reasons. First, presence of the thermal vias prevents an area of the conductor of the power system from being increased when the thermal vias are electrically independent and insulated from the other conductive patterns or pattern connecting vias (through holes) or when all the thermal vias are connected together so as to be at the same potential. Furthermore, there is a definite limit when a number of thermal vias are formed in the remaining area. Second, when all the thermal vias are electrically connected together, the resistance and the inductance (loop inductance) at the power system cannot be reduced though the resistance at the ground system is reduced. Furthermore, the capacitance between the power supply and the ground cannot be provided in a portion beneath the semiconductor chip mounting portion, in which portion the thermal vias are formed.